Publications

Leakage Power & Reliability


2015

  • Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang, Modeling and Optimization of Low Power Resonant Clock Mesh , in Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015, pp.478-483. pdf

2014

  • Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie, PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.33, No.11, 2014, pp.1644-1656. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang, Statistical analysis of random telegraph noise in digital circuits. , in Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp.161-166. pdf slide
  • Xiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang, Run-time technique for simultaneous aging and power optimization in GPGPUs , in Proceedings of the 51st Design Automation Conference (DAC), 2014, pp.168:1-168:6. pdf slide

2013

  • Xiaoming Chen, Yu Wang, Huazhong Yang, Yuan Xie, Yu Cao, Assessment of Circuit Optimization Techniques Under NBTI. , in IEEE Design & Test (D&T), vol.30, No.6, 2013, pp.40-49. pdf
  • Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits , in IET Circuits, Devices & Systems , vol.7, No.5, 2013, pp.273-282. pdf
  • Yaojun Zhang and Bayram, I. and Yu Wang and Hai Li and Yiran Chen, ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications , in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, pp.9-16. pdf

2012

  • Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, Variation-aware supply voltage assignment for simultaneous power and aging optimization , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.20, No.11, 2012, pp.2143-2147. pdf
  • Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, Parametric yield-driven resource binding in high-level synthesis with multi-V th/V dd library and device sizing , in Journal of Electrical and Computer Engineering (JECE), vol.2012, No.3, 2012, pp.3. pdf
  • Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie, PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method , in Proceedings of the 49th Annual Design Automation Conference (DAC), 2012, pp.1191-1196. pdf
  • Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen, Improving energy efficiency of write-asymmetric memories by log style write , in Proceedings of the ACM/IEEE international symposium on Low power electronics and design (ISLPED), 2012, pp.173-178.
  • Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012, pp.183-188. pdf

2011

  • Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling and the impact of standby leakage reduction techniques on circuit performance degradation , in Dependable and secure computing, IEEE transactions on (TDSC), vol.8, No.5, 2011, pp.756-769. pdf
  • Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang, Power gating aware task scheduling in mpsoc , in Very Large Scale Integration Systems, IEEE Transactions on (TVLSI), vol.19, No.10, 2011, pp.1801-1812.
  • Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, Leakage power and circuit aging cooptimization by gate replacement techniques , in Very Large Scale Integration Systems, IEEE Transactions on (TVLSI), vol.19, No.4, 2011, pp.615-628. pdf
  • Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto, Network flow-based simultaneous retiming and slack budgeting for low power design , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.473-478. pdf
  • Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Ch, Vikas ra, Yuchun Ma, Huazhong Yang, Circuit-level delay modeling considering both TDDB and NBTI , in Proceedings of the 12th International Symposium on Quality Electronic Design (ISQED), 2011, pp.14-21. pdf
  • Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang, A hardware-software collaborated method for soft-error tolerant mpsoc , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, pp.260-265. pdf
  • Hong Luo, Yu Wang, J Velamala, Yu Cao, Yuan Xie, Huazhong Yang, The impact of correlation between NBTI and TDDB on the performance of digital circuits , in Proceedings of the IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, pp.1-4. pdf

2010

  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, Output remapping technique for critical paths soft-error rate reduction , in IET Computers & Digital Techniques, vol.4, No.4, 2010, pp.325-333. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, SERSim: a soft error rate simulator and a case study for a 32-bit OpenRisc 1200 microprocessor , in International Journal of Electronics, vol.97, No.4, 2010, pp.441-455.
  • Qian Ding, Yu Wang, Rong Luo, Hui Wang, Huazhong Yang, Soft error generation analysis in combinational logic circuits , in Journal of Semiconductors, vol.31, No.9, 2010, pp.095015.
  • Yibo Chen, Yuan Xie, Yu Wang, Andres Takach, Parametric yield driven resource binding in behavioral synthesis with multi-V th/V dd library , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.781-786. pdf

2009

  • Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling techniques in digital circuits , in IEICE transactions on electronics , vol.92, No.6, 2009, pp.875-886.
  • Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan, New-age: a negative bias temperature instability-estimation framework for microarchitectural components , in International journal of parallel programming (IJPP), vol.37, No.4, 2009, pp.417-431.
  • Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Software tools for analyzing NBTI-induced digital circuit degradation , in Journal of Electronics (China), vol.26, No.5, 2009, pp.715-719.
  • Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan, A framework for estimating NBTI degradation of microarchitectural components , in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2009, pp.455-460. pdf
  • Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, Gate replacement techniques for simultaneous leakage and aging optimization , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2009, pp.328-333. pdf slide
  • Bo Zhao, Yu Wang, Huazhong Yang, Hui Wang, The NBTI impact on RF front end in wireless sensor networks , in Proceedings of the IEEE Circuits and Systems International Conference on Testing and Diagnosis (ICTD), 2009, pp.1-4. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, Variation-aware supply voltage assignment for minimizing circuit degradation and leakage , in Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design (ISLPED), 2009, pp.39-44. pdf slide
  • Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang, On the efficacy of input Vector Control to mitigate NBTI effects and leakage power , in Proceedings of the Quality of Electronic Design (ISQED), 2009, pp.19-26. pdf
  • Balaji Vaidyanathan, Anthony S Oates, Yuan Xie, Yu Wang, NBTI-aware statistical circuit delay assessment. , in Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2009, pp.13-18. pdf
  • Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang, On-line mpsoc scheduling considering power gating induced power/ground noise , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009, pp.109-114. pdf

Before 2008 Ends

  • Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang, Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.16, No.9, 2008, pp.1101-1113. pdf
  • Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang, A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in udvs application , in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2008, pp.304-309. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, Output remapping technique for soft-error rate reduction in critical paths , in Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED), 2008, pp.74-77. pdf
  • Xukai Shen, Yu Wang, Rong Luo, Huazhong Yang, Leakage power reduction through dual V th assignment considering threshold voltage variation , in Proceedings of the 7th International Conference on ASIC (ASICON), 2007, pp.1122-1125. pdf
  • Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2007, pp.546-551. pdf
  • Ku He, Rong Luo, Yu Wang, A power gating scheme for ground bounce reduction during mode transition , in Proceedings of the 25th International Conference on Computer Design (ICCD), 2007, pp.388-394.
  • Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Modeling of PMOS NBTI effect considering temperature variation , in Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED), 2007, pp.139-144. pdf
  • Huazhong Yang, Yu Wang, Hai Lin, Rong Luo, Hui Wang, Fine-grain Sleep Transistor Insertion for Leakage Reduction , in Chinese Journal of Semiconductors, vol.27, No.2, 2006, pp.258-265.
  • Yu Wang, Huazhong Yang, Hui Wang, Signal-Path-Level Dual-V~t Assignment for Leakage Power Reduction , in Journal of Circuits, Systems, and Computers (JCSC), vol.15, No.02, 2006, pp.197-216. pdf
  • Yongpan Liu, Yu Wang, Feng Zhang, Rong Luo, Hui Wang, A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2006, pp.968-971. pdf
  • Yu Wang, Hui Wang, Huazhong Yang, Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2006, pp.964-967. pdf
  • Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang, Simultaneous fine-grain sleep transistor placement and sizing for leakage optimization , in Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), 2006, pp.723-728. pdf

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