2D/3D EDA Tools & Design Methodologies

Low Power Design and Reliability Analysis

As technology scales, leakage power and aging have become two most important issues for nano-scale integrated circuits. Previous studies only focused on one of the two issues. In addition, modern embedded applications have brought great requirements of low power and high reliability. We have investigated the relation between leakage power and aging, and pointed out that reducing leakage power and extending lifetime are contradictory. Consequently, we have proposed that leakage power and aging should be optimized simultaneously. We have also developed several cooptimization techniques, such as input vector control, internal node control, supply voltage control, etc.

We have also studied negative bias temperature bias modeling, random telegraph noise, soft error, power noise, etc.

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Publications

  • Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang, Modeling and Optimization of Low Power Resonant Clock Mesh , in Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015, pp.478-483. pdf
  • Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie, PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.33, No.11, 2014, pp.1644-1656. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang, Statistical analysis of random telegraph noise in digital circuits. , in Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp.161-166. pdf slide
  • Xiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang, Run-time technique for simultaneous aging and power optimization in GPGPUs , in Proceedings of the 51st Design Automation Conference (DAC), 2014, pp.1-6. pdf slide
  • Xiaoming Chen, Yu Wang, Huazhong Yang, Yuan Xie, Yu Cao, Assessment of Circuit Optimization Techniques Under NBTI. , in IEEE Design & Test (D&T), vol.30, No.6, 2013, pp.40-49. pdf
  • Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits , in IET Circuits, Devices & Systems , vol.7, No.5, 2013, pp.273-282. pdf
  • Yaojun Zhang and Bayram, I. and Yu Wang and Hai Li and Yiran Chen, ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications , in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, pp.9-16. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, Variation-aware supply voltage assignment for simultaneous power and aging optimization , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.20, No.11, 2012, pp.2143-2147. pdf
  • Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, Parametric yield-driven resource binding in high-level synthesis with multi-V th/V dd library and device sizing , in Journal of Electrical and Computer Engineering (JECE), vol.2012, No.3, 2012, pp.3. pdf
  • Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie, PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method , in Proceedings of the 49th Annual Design Automation Conference (DAC), 2012, pp.1191-1196. pdf
  • Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen, Improving energy efficiency of write-asymmetric memories by log style write , in Proceedings of the ACM/IEEE international symposium on Low power electronics and design (ISLPED), 2012, pp.173-178.
  • Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012, pp.183-188. pdf
  • Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling and the impact of standby leakage reduction techniques on circuit performance degradation , in Dependable and secure computing, IEEE transactions on (TDSC), vol.8, No.5, 2011, pp.756-769.
  • Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang, Power gating aware task scheduling in mpsoc , in Very Large Scale Integration Systems, IEEE Transactions on (TVLSI), vol.19, No.10, 2011, pp.1801-1812.
  • Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, Leakage power and circuit aging cooptimization by gate replacement techniques , in Very Large Scale Integration Systems, IEEE Transactions on (TVLSI), vol.19, No.4, 2011, pp.615-628. pdf
  • Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto, Network flow-based simultaneous retiming and slack budgeting for low power design , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.473-478. pdf
  • Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Ch, Vikas ra, Yuchun Ma, Huazhong Yang, Circuit-level delay modeling considering both TDDB and NBTI , in Proceedings of the 12th International Symposium on Quality Electronic Design (ISQED), 2011, pp.1-8. pdf
  • Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang, A hardware-software collaborated method for soft-error tolerant mpsoc , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, pp.260-265. pdf
  • Hong Luo, Yu Wang, J Velamala, Yu Cao, Yuan Xie, Huazhong Yang, The impact of correlation between NBTI and TDDB on the performance of digital circuits , in Proceedings of the IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, pp.1-4. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, Output remapping technique for critical paths soft-error rate reduction , in IET Computers & Digital Techniques, vol.4, No.4, 2010, pp.325-333. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, SERSim: a soft error rate simulator and a case study for a 32-bit OpenRisc 1200 microprocessor , in International Journal of Electronics, vol.97, No.4, 2010, pp.441-455.
  • Qian Ding, Yu Wang, Rong Luo, Hui Wang, Huazhong Yang, Soft error generation analysis in combinational logic circuits , in Journal of Semiconductors, vol.31, No.9, 2010, pp.095015.
  • Yibo Chen, Yuan Xie, Yu Wang, Andres Takach, Parametric yield driven resource binding in behavioral synthesis with multi-V th/V dd library , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.781-786. pdf
  • Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling techniques in digital circuits , in IEICE transactions on electronics , vol.92, No.6, 2009, pp.875-886.
  • Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan, New-age: a negative bias temperature instability-estimation framework for microarchitectural components , in International journal of parallel programming (IJPP), vol.37, No.4, 2009, pp.417-431.
  • Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Software tools for analyzing NBTI-induced digital circuit degradation , in Journal of Electronics (China), vol.26, No.5, 2009, pp.715-719.
  • Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan, A framework for estimating NBTI degradation of microarchitectural components , in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2009, pp.455-460. pdf
  • Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, Gate replacement techniques for simultaneous leakage and aging optimization , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2009, pp.328-333. pdf slide
  • Bo Zhao, Yu Wang, Huazhong Yang, Hui Wang, The NBTI impact on RF front end in wireless sensor networks , in Proceedings of the IEEE Circuits and Systems International Conference on Testing and Diagnosis (ICTD), 2009, pp.1-4. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, Variation-aware supply voltage assignment for minimizing circuit degradation and leakage , in Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design (ISLPED), 2009, pp.39-44. pdf slide
  • Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang, On the efficacy of input Vector Control to mitigate NBTI effects and leakage power , in Proceedings of the Quality of Electronic Design (ISQED), 2009, pp.19-26. pdf
  • Balaji Vaidyanathan, Anthony S Oates, Yuan Xie, Yu Wang, NBTI-aware statistical circuit delay assessment. , in Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2009, pp.13-18. pdf
  • Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang, On-line mpsoc scheduling considering power gating induced power/ground noise , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009, pp.109-114. pdf
  • Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang, Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.16, No.9, 2008, pp.1101-1113. pdf
  • Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang, A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in udvs application , in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2008, pp.304-309. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, Output remapping technique for soft-error rate reduction in critical paths , in Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED), 2008, pp.74-77. pdf
  • Xukai Shen, Yu Wang, Rong Luo, Huazhong Yang, Leakage power reduction through dual V th assignment considering threshold voltage variation , in Proceedings of the 7th International Conference on ASIC (ASICON), 2007, pp.1122-1125. pdf
  • Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2007, pp.1-6. pdf
  • Ku He, Rong Luo, Yu Wang, A power gating scheme for ground bounce reduction during mode transition , in Proceedings of the 25th International Conference on Computer Design (ICCD), 2007, pp.388-394.
  • Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Modeling of PMOS NBTI effect considering temperature variation , in Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED), 2007, pp.139-144. pdf
  • Huazhong Yang, Yu Wang, Hai Lin, Rong Luo, Hui Wang, Fine-grain Sleep Transistor Insertion for Leakage Reduction , in Chinese Journal of Semiconductors, vol.27, No.2, 2006, pp.258-265.
  • Yu Wang, Huazhong Yang, Hui Wang, Signal-Path-Level Dual-V~t Assignment for Leakage Power Reduction , in Journal of Circuits, Systems, and Computers (JCSC), vol.15, No.02, 2006, pp.197-216. pdf
  • Yongpan Liu, Yu Wang, Feng Zhang, Rong Luo, Hui Wang, A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2006, pp.968-971. pdf
  • Yu Wang, Hui Wang, Huazhong Yang, Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2006, pp.964-967. pdf
  • Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang, Simultaneous fine-grain sleep transistor placement and sizing for leakage optimization , in Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), 2006, pp.723-728. pdf

High-speed Circuit Simulation

The simulation program with integrated circuit emphasis (SPICE) is widely used in IC designs and verifications. The sparse matrix solver is a bottleneck in SPICE-like circuit simulators. It is difficult to parallelize the solver because of the high data dependency during the numeric LU factorization and the irregular structure of circuit matrices. We have proposed an adaptive sparse matrix solver called NICSLU, which uses a multithreaded parallel LU factorization algorithm on shared-memory computers with multicore/multisocket central processing units to accelerate circuit simulation. We have developed a novel task description, partitioning and scheduling framework, to explore parallelism and reduce the parallel overhead as much as possible. NICSLU can be used in all the SPICE-like circuit simulators. NICSLU has the following features:

  1. NICSLU is based on the sparse left-looking algorithm, which is suitable for cache-based machines.
  2. NICSLU automatically selects column-column or supernode-column algorithm to fit the sparsity of matrices.
  3. NICSLU automatically judges if a matrix is suitable for parallel factorization.
  4. NICSLU specially supports the case that requires many factorizations with the same nonzero pattern (it is called re-factorization), which is very useful for the iterations in circuit simulation.

NICSLU is more than 8X faster than KLU, when NICSLU uses 16 threads. When comparing with PARDISO, NICSLU is about 3X faster than PARDISO when NICSLU and PARDISO use the same number of threads. NICSLU can be downloaded from http://nicslu.weebly.com.

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Publications

  • Xiaoming Chen, Yu Wang, Huazhong Yang, Parallel Sparse Direct Solver for Integrated Circuit Simulation , 2017.
  • Xiaoming Chen, Lixue Xia, Yu Wang, Huazhong Yang, Sparsity-Oriented Sparse Solver Design for Circuit Simulation , in DATE, 2016, pp.1580-1585. pdf slide
  • Xiaoming Chen, Ling Ren, Yu Wang, Huazhong Yang, GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling , in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.26, No.3, 2015, pp.786-795. pdf
  • Xiaoming Chen, Yu Wang, Huazhong Yang, A Fast Parallel Sparse Solver for SPICE-based Circuit Simulators , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.205-210. pdf slide
  • Xiaoming Chen, Yu Wang, Huazhong Yang, NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation. , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.32, No.2, 2013, pp.261-274. pdf
  • Xiaoming Chen, Du Su, Yu Wang, Huazhong Yang, Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation , in Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms (IA^3), 2013, pp.8. pdf slide
  • Xiaoming Chen, Yu Wang, Huazhong Yang, An adaptive LU factorization algorithm for parallel circuit simulation , in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp.359-364. pdf slide
  • Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong Yang, Sparse LU factorization for parallel circuit simulation on GPU , in Proceedings of the 49th Annual Design Automation Conference (DAC), 2012, pp.1125-1130. pdf slide
  • Xiaoming Chen, Yu Wang, Huazhong Yang, Parallel Circuit Simulation on Multi/Many-core Systems , in Proceedings of the IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012, pp.2530-2533. pdf
  • Xiaoming Chen, Wei Wu, Yu Wang, Hao Yu, Huazhong Yang, An escheduler-based data dependence analysis and task scheduling for parallel circuit simulation , in Circuits and Systems II: Express Briefs, IEEE Transactions on (TCASII), vol.58, No.10, 2011, pp.702-706. pdf
  • Wei Wu,Yi Shan,Xiaoming Chen,Yu Wang,Huazhong Yang, FPGA accelerated parallel sparse matrix factorization for circuit simulations , in Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications (ARC), 2011, pp.302-315. pdf

3D IC Design Exploration

Three-dimensional (3D) integration technology has been proposed as a promising technology to provide small footprint, reduced wire-length, and the capability of heterogeneous integration. Different from the 2D IC design, the clock network and P/G network designs are much more complex for the 3D ICs. We have proposed the whitespace-aware and TSV-aware 3D clock network synthesis algorithms by considering the limited whitespaces for TSV-insertion, and the relative severe parasitic/coupling effect of TSVs. In addition, analysis of the complex 3D P/G network is much time-consumed. We have studied the hierarchical simulation method for 3D P/G network (HS3DPG). The hierarchical method HS3DPG can be 6.5 times faster than the direct full network simulation.

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The whitespace-aware 3D CTS flow
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Simulation flow of HS3DPG

Most of the previous work mainly focuses on 3D digital IC design. Meanwhile, another advantage of 3D stacking, heterogeneous integration, has not been fully exploited. In particular, 3D IC is a good candidate to address the design issues in conventional analog/digital mixed-signal IC designs. In this project, we mainly focus on modeling and analyzing the impacts of through silicon vias (TSVs) on mixed-signal ICs. Based on the analysis, a set of design methodologies for 3D mixed-signal ICs are pro-posed. The design methodologies are verified with a case study, in which a 12-bit successive approximation register analog-to-digital converter (SAR ADC) is re-designed by partitioning it into three stacked layers for 3D integration. The experimental results demonstrate the superiority of 3D heterogeneous integration in power reduction and performance improvement.

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12-bit ADC architecture and 3D partitioning
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Layouts of the 3D 12-bit SAR ADC

Publications

  • Yu Wang, Song Yao, Shuai Tao, Xiaoming Chen, Yuchun Ma, Yiyu Shi, Huazhong Yang, HS3DPG: Hierarchical Simulation for 3D P/G Network , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.23, No.10, 2015, pp.2307-2311. pdf
  • Wulong Liu, Yu Wang, Guoqing Chen, Yuchun Ma, Yuan Xie, Huazhong Yang, Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.23, No.9, 2015, pp.1842 - 1853. pdf
  • Wulong Liu, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang, On-chip hybrid power supply system for wireless sensor nodes , in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol.10, No.3, 2014, pp.23. pdf
  • Wulong Liu, Yu Wang, Yu Wang, Xue Feng, Yuan Xie, Yidong Huang, Huazhong Yang, Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects , in IEEE Design & Test, vol.31, No.5, 2014, pp.28-35. pdf
  • Wulong Liu, Guoqing Chen, Xue Han, Yu Wang, Yuan Xe, Huazhong Yang, Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case , in Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, pp.1-6. pdf
  • Song Yao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang, Efficient region-aware P/G TSV planning for 3D ICs , in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), 2014, pp.171-178. pdf
  • Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang, HS3DPG: Hierarchical simulation for 3D P/G network , in Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, pp.509-514. pdf
  • Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang, TSV-aware topology generation for 3D clock tree synthesis , in Proceeding of the 14th International Symposium on Quality Electronic Design (ISQED), 2013, pp.300-307. pdf
  • Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang, Whitespace-aware TSV arrangement in 3D clock tree synthesis , in Proceeding of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013, pp.115-120. pdf
  • Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian, RALP: Reconvergence-aware layer partitioning for 3D FPGAs. , in Proceeding of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013, pp.1-6. pdf
  • Wulong Liu, Tao Zhang, Xue Han, Yu Wang, Yuan Xie, Huazhong Yang, Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 8-bit SAR ADC Design Case , in 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Work-in-Progress (WIP), 2013. pdf
  • Jing Xie, Yu Wang, Yuan Xie, Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs , in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp.738-743. pdf
  • Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie, Thermal-aware power network design for ir drop reduction in 3d ics , in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp.47-52. pdf
  • Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong, Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs , in IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (IEICE), vol.94, No.12, 2011, pp.2490-2498. pdf
  • Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong, Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.261-266. pdf
  • Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang, On-chip Hybrid Power Supply System for Wireless Sensor Nodes , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.23:1--23:22. pdf
  • Shouchun Tao, Jia Liu, Yuchun Ma, Zhigang He, Ning Xu, Yu Wang, Xianlong Hong, An ILP algorithm for voltage-island generation considering temperature in 3D-Ics , in Proceddings of the International Conference on Electric Information and Control Engineering (ICEICE), 2011, pp.3950-3953. pdf
  • Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang, Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.169-174. pdf
  • Shuai Tao, Yu Wang, Jiang Xu, Yuchun Ma, Yuan Xie, Huazhong Yang, Simulation and analysis of P/G noise in TSV based 3D MPSoC , in Proceedings of the International Conference on Green Circuits and Systems (ICGCS), 2010, pp.573-577. pdf
  • Yuchun Ma, Kan Wang, Sheqin Dong, Yu Wang, Xianlong Hong, Thermal effects of leakage power in 3D ICs , in Proceedings of the International Conference on Green Circuits and Systems (ICGCS), 2010, pp.578-583. pdf
  • Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong, Thermal-aware incremental floorplanning for 3D ICs based on MILP formulation , in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences , vol.92, No.12, 2009, pp.2979-2989.
  • Balaji Vaidyanathan, Yu Wang, Yuan Xie, Cost-aware lifetime yield analysis of heterogeneous 3D on-chip cache , in Proceedings of the IEEE International Workshop on Memory Technolog (MTDT), 2009, pp.65-70. pdf

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