Feature size of the CMOS transistor keeps going down to reduce the area and power of integrated circuits. A lot of side effects come along with the scaling down, how to build up a reliable and low power system based on un-reliable nano-scale devices become a critical problem. We focus on three main topics:
- Leakage power and reliability (especially aging) aware design methodology
- Fast/Parallel Circuit Simulation
- Heterogenous Integration for 3D IC.
Integration of more processing element and memory is another way to integrate more transistors, so that one single IC can have more functions. However, how to map different applications to multi/many core system or directly to transistors (by FPGA or ASIC), and then make these silicon work in a more efficient way bring us opportunities to research in the application specific hardware computing area. We mainly focus on the basic key operations: matrix operations, graph theoretical algorithms, and etc. We category our research according to different applications or computing frameworks:
It seems that we can not get orders of gains in the power efficiency by just putting more transistors in one chip, we need some changes in the computational model and the devices simultaneously.
So in this direction, we look into the neuroscience area a little bit, and using our hardware computing techniques to help the neuroscientists and doctors to reveal more interesting insights from the Imaging based techniques (XMRI).
On the other hand, we are looking at new devices, such as RRAM/Memristor to build new circuit components, which can reduce orders of computational complexity in a different layer comparing with the algorithm optimization for some specific application domains.