Yu Wang (汪玉)


Yu Wang is an Associate Prof. in EE Dept, Tsinghua University. He received his B.S. degree in Tsinghua University, China in 2002, and then Ph.D. degree with honor in NICS Group, Electronics Engineering Department, Tsinghua University in 2007, supervised by Prof. Huazhong Yang (Tsinghua University) and Prof. Yuan Xie (Penn. State University). Dr. Wang's research interest ranges from EDA to Architecture/Application Co-design, mainly focuses on Energy Efficient Hardware Computing System Design, Brain Inspired Computing System on Emerging Devices, Parallel Circuit Analysis, Low Power/Reliability-aware System Design Methodology.

Contact

Address: Room 4-303, Rohm Building, E.E. Dept., Tsinghua University, Beijing, China
Email: yu-wang☺tsinghua·eduNOSPAMMING·cn
Phone: +86-10-62772966
Fax: +86-10-62770317

Selected Publications


Journal Articles

  • Huizi Mao, Song Yao, Tianqi Tang, Boxun Li, Jun Yao, Yu Wang, Towards Real-Time Object Detection on Embedded Systems , to appear in IEEE Transactions on Emerging Topics in Computing, 2016.
  • Haixiao Du, Xuhong Liao, Mingrui Xia, Qixiang Lin, Gushu Li, Yuze Chi, Huazhong Yang, Yu Wang, Yong He, Test-Retest Reliability of Graph Metrics in High-Resolution Functional Connectomics: A Resting-State Functional MRI Study , in CNS Neuroscience & Therapeutics, vol.21, No.10, 2015, pp.802-816. pdf
  • Boxun Li, Peng Gu, Yi Shan, Yu Wang, Yiran Chen, Huazhong Yang, RRAM-based Analog Approximate Computing , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, No.12, 2015, pp.1905-1917. pdf
  • Wenqiang Wang, Jing Yan, Ningyi Xu, Yu Wang, Feng-Hsiung Hsu, Real-time High-quality Stereo Vision System in FPGA , in IEEE Transactions on Circuits and Systems for Video Technology (TCSVT), vol.25, No.10, 2015, pp.1696-1708. pdf
  • Xiaoming Chen, Ling Ren, Yu Wang, Huazhong Yang, GPU-Accelerated Sparse LU Factorization for Circuit Simulation with Performance Modeling , in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.26, No.3, 2015, pp.786-795. pdf
  • Yu Wang, Song Yao, Shuai Tao, Xiaoming Chen, Yuchun Ma, Yiyu Shi, Huazhong Yang, HS3DPG: Hierarchical Simulation for 3D P/G Network , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.23, No.10, 2015, pp.2307-2311. pdf
  • Wulong Liu, Yu Wang, Guoqing Chen, Yuchun Ma, Yuan Xie, Huazhong Yang, Whitespace-Aware TSV Arrangement in 3-D Clock Tree Synthesis , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.23, No.9, 2015, pp.1842 - 1853. pdf
  • Wulong Liu, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang, On-chip hybrid power supply system for wireless sensor nodes , in ACM Journal on Emerging Technologies in Computing Systems (JETC), vol.10, No.3, 2014, pp.23. pdf
  • Yi Shan, Yuchen Hao, Wenqiang Wang, Yu Wang, Xu Chen, Huazhong Yang, Wayne Luk, Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region , in ACM Transactions on Embedded Computing Systems (TECS), vol.13, No.4s, 2014, pp.132:1--132:24. pdf
  • Wulong Liu, Yu Wang, Yu Wang, Xue Feng, Yuan Xie, Yidong Huang, Huazhong Yang, Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects , in IEEE Design & Test, vol.31, No.5, 2014, pp.28-35. pdf
  • Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie, PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.33, No.11, 2014, pp.1644-1656. pdf
  • Hong Zhang, Xue Feng, Boxun Li, Yu Wang, Kaiyu Cui, Fang Liu, Weibei Dou, and Yidong Huang, Integrated photonic reservoir computing based on hierarchical time-multiplexing structure , in Optical Express, vol.22, No.25, 2014, pp.31356-31370. pdf
  • Xiaoming Chen, Yu Wang, Huazhong Yang, Yuan Xie, Yu Cao, Assessment of Circuit Optimization Techniques Under NBTI. , in IEEE Design & Test (D&T), vol.30, No.6, 2013, pp.40-49. pdf
  • Xiaoming Chen, Yu Wang, Huazhong Yang, NICSLU: An Adaptive Sparse Matrix Solver for Parallel Circuit Simulation. , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.32, No.2, 2013, pp.261-274. pdf
  • Weichen Liu, Yu Wang, Xuan Wang, Jiang Xu, Huazhong Yang, On-Chip Sensor Network for Efficient Management of Power Gating-Induced Power/Ground Noise in Multiprocessor System on Chip , in IEEE Transactions on Parallel and Distributed Systems (TPDS), vol.24, No.4, 2013, pp.767-777. pdf
  • Xiaoming Chen, Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, Evaluation and mitigation of performance degradation under random telegraph noise for digital circuits , in IET Circuits, Devices & Systems , vol.7, No.5, 2013, pp.273-282. pdf
  • Ruining He, Guoqiang Liang, Yuchun Ma, Yu Wang, Jinian Bian, Unification of PR Region floorplanning and Fine-Grained Placement for Dynamic Partially Reconfigurable FPGAs , in Journal of Circuits, Systems, and Computers (JCSC), vol.22, No.04, 2013, pp.1350020.
  • Yu Wang, Haixiao Du, Mingrui Xia, Ling Ren, Mo Xu, Teng Xie, Gaolang Gong, Ningyi Xu, Huazhong Yang, Yong He, A Hybrid CPU-GPU Accelerated Framework for Fast Mapping of High-Resolution Human Brain Connectome , in PloS one, vol.8, No.9, 2013, pp.e62789. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, Variation-aware supply voltage assignment for simultaneous power and aging optimization , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.20, No.11, 2012, pp.2143-2147. pdf
  • Yibo Chen, Yu Wang, Yuan Xie, Andres Takach, Parametric yield-driven resource binding in high-level synthesis with multi-V th/V dd library and device sizing , in Journal of Electrical and Computer Engineering (JECE), vol.2012, No.3, 2012, pp.3. pdf
  • Jing Yan, Ning-YI Xu, Xiong-FEI Cai, Rui Gao, Yu Wang, Rong Luo, Feng-HSIUNG Hsu, An FPGA-based accelerator for LambdaRank in Web search engines , in ACM Transactions on Reconfigurable Technology and Systems (TRETS), vol.4, No.3, 2011, pp.25:1-25:19. pdf
  • Xiaoming Chen, Wei Wu, Yu Wang, Hao Yu, Huazhong Yang, An escheduler-based data dependence analysis and task scheduling for parallel circuit simulation , in Circuits and Systems II: Express Briefs, IEEE Transactions on (TCASII), vol.58, No.10, 2011, pp.702-706. pdf
  • Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling and the impact of standby leakage reduction techniques on circuit performance degradation , in Dependable and secure computing, IEEE transactions on (TDSC), vol.8, No.5, 2011, pp.756-769.
  • Yu Wang, Jiang Xu, Yan Xu, Weichen Liu, Huazhong Yang, Power gating aware task scheduling in mpsoc , in Very Large Scale Integration Systems, IEEE Transactions on (TVLSI), vol.19, No.10, 2011, pp.1801-1812.
  • Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, Leakage power and circuit aging cooptimization by gate replacement techniques , in Very Large Scale Integration Systems, IEEE Transactions on (TVLSI), vol.19, No.4, 2011, pp.615-628. pdf
  • Kan Wang, Sheqin Dong, Yuchun Ma, Yu Wang, Xianlong Hong, Jason Cong, Leakage-Aware TSV-Planning with Power-Temperature-Delay Dependence in 3D ICs , in IEICE TRANSACTIONS on Fundamentals of Electronics, Communications and Computer Sciences (IEICE), vol.94, No.12, 2011, pp.2490-2498. pdf
  • Sheng-Qing Shi, Kai Chen, Yu Wang, Rong Luo, Node importance analysis in complex networks based on hardware computing , in Dianzi Yu Xinxi Xuebao (Journal of Electronics and Information Technology), vol.33, No.10, 2011, pp.2536-2540.
  • Guangming Yu, Yu Wang, Huazhong Yang, Hui Wang, Fast-locking all-digital phase-locked loop with digitally controlled oscillator tuning word estimating and presetting , in IET Circuits, Devices & Systems , vol.4, No.3, 2010, pp.207-217.
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, Output remapping technique for critical paths soft-error rate reduction , in IET Computers & Digital Techniques, vol.4, No.4, 2010, pp.325-333. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, SERSim: a soft error rate simulator and a case study for a 32-bit OpenRisc 1200 microprocessor , in International Journal of Electronics, vol.97, No.4, 2010, pp.441-455.
  • Qian Ding, Yu Wang, Rong Luo, Hui Wang, Huazhong Yang, Soft error generation analysis in combinational logic circuits , in Journal of Semiconductors, vol.31, No.9, 2010, pp.095015.
  • Yuchun Ma, Xin Li, Yu Wang, Xianlong Hong, Thermal-aware incremental floorplanning for 3D ICs based on MILP formulation , in IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences , vol.92, No.12, 2009, pp.2979-2989.
  • Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling techniques in digital circuits , in IEICE transactions on electronics , vol.92, No.6, 2009, pp.875-886.
  • Michael DeBole, Ramakrishnan Krishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan, New-age: a negative bias temperature instability-estimation framework for microarchitectural components , in International journal of parallel programming (IJPP), vol.37, No.4, 2009, pp.417-431.
  • Hong Luo, Yu Wang, Rong Luo, Huazhong Yang, Software tools for analyzing NBTI-induced digital circuit degradation , in Journal of Electronics (China), vol.26, No.5, 2009, pp.715-719.
  • Yu Wang, Ku He, Rong Luo, Hui Wang, Huazhong Yang, Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits , in IEEE Transactions on Very Large Scale Integration Systems (TVLSI), vol.16, No.9, 2008, pp.1101-1113. pdf
  • Huazhong Yang, Yu Wang, Hai Lin, Rong Luo, Hui Wang, Fine-grain Sleep Transistor Insertion for Leakage Reduction , in Chinese Journal of Semiconductors, vol.27, No.2, 2006, pp.258-265.
  • Yu Wang, Huazhong Yang, Hui Wang, Signal-Path-Level Dual-V~t Assignment for Leakage Power Reduction , in Journal of Circuits, Systems, and Computers (JCSC), vol.15, No.02, 2006, pp.197-216. pdf

Conference Papers

  • Sicheng Li, Yu Wang, Hai Li, A Data Locality-aware Design Framework for Reconfigurable Sparse Matrix-Vector Multiplication Kernel , to appear in International Conference On Computer Aided Design (ICCAD), 2016, pp.1-8.
  • Ping Chi, Shuangchen Li, Cong Xu, Tao Zhang, Jishen Zhao, Yongpan Liu, Yu Wang, Yuan Xie, A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory , in The 43rd ACM/IEEE International Symposium on Computer Architecture, 2016, pp.1-14.
  • Kaiyuan Guo, Lingzhi Sui, Jiantao Qiu, Song Yao, Song Han, Yu Wang and Huazhong Yang, Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware , in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, pp.1-4.
  • Wulong Liu, Guoqing Chen, Yu Wang, Huazhong Yang, Modeling and Optimization of Low Power Resonant Clock Mesh , in Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015, pp.478-483. pdf
  • Peng Gu, Boxun Li, Tianqi Tang, Shimeng Yu, Yu Cao, Yu Wang, Huazhong Yang, Technological Exploration of RRAM Crossbar Array For Matrix-Vector Multiplication , in Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015, pp.106-111. pdf
  • Lixue Xia, Rong Luo, Bin Zhao, Yu Wang, Huazhong Yang, An Accurate and Low Cost PM2.5 Estimation Method Based on Artificial Neural Network , in Proceedings of the 20th Asia and South Pacific Design Automation Conference (ASP-DAC), 2015, pp.190-195. pdf
  • Gushu Li, Xiaoming Chen, Guangyu Sun, Henry Hoffmann, Yongpan Liu, Yu Wang, Huazhong Yang, A STT-RAM-based Low-Power Hybrid Register File for GPGPUs , in 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, pp.1-6. pdf
  • Boxun Li, Lixue Xia, Peng Gu, Yu Wang, and Huazhong Yang, Merging the interface: Power, area and accuracy co-optimization for RRAM crossbar-based mixed-signal , in 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, pp.1-6. pdf
  • Xiaoxiao Liu, Mengjie Mao, Beiye Liu, Boxun Li, Hao Jiang, Yu Wang, Mark Barnell, Qing Wu, J. Joshua, Reno: A Highly-efficient Reconfigurable Neuromorphic Computing Accelerator Design , in 52nd ACM/EDAC/IEEE Design Automation Conference (DAC), 2015, pp.1-6.
  • Xiaoming Chen, Yu Wang, Huazhong Yang, A Fast Parallel Sparse Solver for SPICE-based Circuit Simulators , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.205-210. pdf slide
  • Tianqi Tang, Lixue Xia, Boxun Li, Rong Luo, Yu Wang, Yiran Chen, Huangzhong Yang, Spiking Neural Network with RRAM : Can We Use it for Real-World Application? , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2015, pp.860-865. pdf
  • Sicheng Li, Chunpeng Wu, Boxun Li, Yu Wang, Qinru Qiu and Hai Li, FPGA Acceleration for Recurrent Neural Network Language Model , in Proceedings of the IEEE 23rd Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM), 2015, pp.111-118. pdf
  • Xinyu Niu, Wayne Luk, Yu Wang, EURECA: On-Chip Configuration Generation for Effective Dynamic Data Access , in Proceedings of the ACM/SIGDA International Symposium on Field-Programmable Gate Arrays (FPGA), 2015, pp.74-83.
  • Yu Wang, Tianqi Tang, Lixue Xia, Boxun Li, Peng Gu, Hai Li, Yuan Xie, Huazhong Yang, Energy Efficient RRAM Spiking Neural Network for Real Time Classification , in Proceedings of the 25th Edition on Great Lakes Symposium on VLSI (GLSVLSI), 2015, pp.189-194. pdf
  • Xiaolong Xie, Yun Liang, Yu Wang, Guangyu Sun, Tao Wang, Coordinated Static and Dynamic Cache Bypassing for GPUs , in Proceedings of the IEEE 21st International Symposium on High Performance Computer Architecture (HPCA) , 2015, pp.76-88. pdf
  • Yung-Hsiang Lu, Alan M. Kadin, Alexander C. Berg, Thomas M. Conte, Erik P. DeBenedictis, Rachit Garg, Ganesh Gingade, Bichlien Hoang, Yongzhen Huang, Boxun Li, Jingyu Liu, Wei Liu, Huizi Mao, Junran Peng, Tianqi Tang, Elie K. Track, Jingqiu Wang, Tao Wang, Yu Wang, Jun Yao, Rebooting Computing and Low-Power Image Recognition Challenge , in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2015, pp.927-932.
  • Xiaoming Chen, Yu Wang, Yu Cao, Huazhong Yang, Statistical analysis of random telegraph noise in digital circuits. , in Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp.161-166. pdf slide
  • Boxun Li, Yuzhi Wang, Yu Wang, Yiran Chen, Huazhong Yang, Training itself: Mixed-signal training acceleration for memristor-based neural network. , in Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp.361-366. pdf
  • Miao Hu, Yu Wang, Qinru Qiu, Yiran Chen, Hai Li, The stochastic modeling of TiO2 memristor and its usage in neuromorphic system design. , in Proceedings of the 19th Asia and South Pacific Design Automation Conference (ASP-DAC), 2014, pp.831-836.
  • Fei Chen, Yi Shan, Yu Zhang, Yu Wang, Hubertus Franke, Xiaotao Chang, Kun Wang, Enabling FPGAs in the Cloud , in Proceedings of the 11th ACM Conference on Computing Frontiers, 2014, pp.3:1-3:10. pdf
  • Wulong Liu, Guoqing Chen, Xue Han, Yu Wang, Yuan Xe, Huazhong Yang, Design methodologies for 3D mixed signal integrated circuits: A practical 12-bit SAR ADC design case , in Proceedings of the 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014, pp.1-6. pdf
  • Xiaoming Chen, Yu Wang, Yun Liang, Yuan Xie, Huazhong Yang, Run-time technique for simultaneous aging and power optimization in GPGPUs , in Proceedings of the 51st Design Automation Conference (DAC), 2014, pp.1-6. pdf slide
  • Boxun Li, Yu Wang, Yiran Chen, Hai Helen Li, Huazhong Yang, ICE: inline calibration for memristor crossbar-based computing engine , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, pp.24-28. pdf
  • Yu Wang, Boxun Li, Rong Luo, Yiran Chen, Ningyi Xu, Huazhong Yang, Energy efficient neural networks for big data analytics , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2014, pp.1-2. pdf
  • Yuliang Sun, Zilong Wang, Sitao Huang, Lanjun Wang, Yu Wang, Rong Luo, Huazhong Yang, Accelerating frequent item counting with fpga , in Proceedings of the ACM/SIGDA international symposium on Field-programmable gate arrays (FPGA), 2014, pp.109-112. pdf
  • Guohao Dai, Yi Shan, Fei Chen, Yu Zhang, Yu Wang, Kun Wang and Huazhong Yang, Online Scheduling for FPGA Computation in the Cloud , in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp.330 - 333. pdf
  • Wenqiang Wang, Kaiyuan Guo, Mengyuan Gu, Yuchun Ma, Yu Wang, A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems , in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp.139 - 146. pdf
  • Boxun Li, Erjin Zhou, Bo Huang, Jiayi Duan, Yu Wang, Ningyi Xu, Jiaxing Zhang, Huazhong Yang, Large Scale Recurrent Neural Network on GPU , in Proceedings of the International Joint Conference on Neural Networks (IJCNN), 2014, pp.4062 - 4069. pdf
  • Tianqi Tang, Rong Luo, Boxun Li, Hai Li, Yu Wang, Huazhong Yang, Energy Efficient Spiking Neural Network Design with RRAM Devices , in Proceedings of the 14th International Symposium on Integrated Circuits (ISIC), 2014, pp.268 - 271. pdf
  • Song Yao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yuan Xie, Huazhong Yang, Efficient region-aware P/G TSV planning for 3D ICs , in Proceedings of the 15th International Symposium on Quality Electronic Design (ISQED), 2014, pp.171-178. pdf
  • Shuai Tao, Xiaoming Chen, Yu Wang, Yuchun Ma, Yiyu Shi, Hui Wang, Huazhong Yang, HS3DPG: Hierarchical simulation for 3D P/G network , in Proceedings of the 18th Asia and South Pacific Design Automation Conference (ASP-DAC), 2013, pp.509-514. pdf
  • Xiang Chen, Ji Zhu, Ziyu Wen, Yu Wang, Huazhong Yang, BER Guaranteed Optimization and Implementation of Parallel Turbo Decoding on GPU , in Proceedings of the 8th International ICST Conference on Communications and Networking in China (CHINACOM), 2013, pp.183-188.
  • Zilong Wang, Sitao Huang, Lanjun Wang, Hao Li, Yu Wang, Huazhong Yang, Accelerating subsequence similarity search based on dynamic time warping distance with FPGA , in Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays (FPGA), 2013, pp.53-62.
  • Xinyu Niu, José Gabriel F. Coutinho, Yu Wang and Wayne Luk, Dynamic Stencil: Effective Exploitation of Run-time Resources in Reconfigurable Clusters , in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp.214-221. pdf
  • Wenqiang Wang, Jing Yan, Ning-Yi Xu, Yu Wang and Feng-Hsiung Hsu, A Real-time High-quality Stereo Vision System on FPGA , in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2013, pp.358-361. pdf
  • Sitao Huang, Guohao Dai, Yuliang Sun, Zilong Wang, Yu Wang, Huazhong Yang, DTW-Based Subsequence Similarity Search on AMD Heterogeneous Computing Platform , in Proceedings of the IEEE 10th International Conference on High Performance Computing and Communications & IEEE International Conference on Embedded and Ubiquitous Computing (HPCCEUC), 2013, pp.1054-1063. pdf
  • Xiaoming Chen, Du Su, Yu Wang, Huazhong Yang, Nonzero pattern analysis and memory access optimization in GPU-based sparse LU factorization for circuit simulation , in Proceedings of the 3rd Workshop on Irregular Applications: Architectures and Algorithms (IA^3), 2013, pp.8. pdf slide
  • Yaojun Zhang and Bayram, I. and Yu Wang and Hai Li and Yiran Chen, ADAMS: Asymmetric Differential STT-RAM Cell Structure for Reliable and High-performance Applications , in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2013, pp.9-16. pdf
  • Boxun Li, Yi Shan, Miao Hu, Yu Wang, Yiran Chen, Huazhong Yang, Memristor-based approximated computation , in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013, pp.242-247. pdf
  • Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Yuan Xie, Jinguo Quan, Huazhong Yang, TSV-aware topology generation for 3D clock tree synthesis , in Proceeding of the 14th International Symposium on Quality Electronic Design (ISQED), 2013, pp.300-307. pdf
  • Xin Li, Wulong Liu, Haixiao Du, Yu Wang, Yuchun Ma, Huazhong Yang, Whitespace-aware TSV arrangement in 3D clock tree synthesis , in Proceeding of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2013, pp.115-120. pdf
  • Qingyu Liu, Yuchun Ma, Yu Wang, Wayne Luk, Jinian Bian, RALP: Reconvergence-aware layer partitioning for 3D FPGAs. , in Proceeding of the International Conference on Reconfigurable Computing and FPGAs (ReConFig), 2013, pp.1-6. pdf
  • Wulong Liu, Tao Zhang, Xue Han, Yu Wang, Yuan Xie, Huazhong Yang, Design Methodologies for 3D Mixed Signal Integrated Circuits: a Practical 8-bit SAR ADC Design Case , in 51st ACM/EDAC/IEEE Design Automation Conference (DAC) Work-in-Progress (WIP), 2013. pdf
  • Brahim Betkaoui, Yu Wang, David B Thomas, Wayne Luk, A reconfigurable computing approach for efficient and scalable parallel graph exploration , in Proceedings of the IEEE 23rd International Conference on Application-Specific Systems, Architectures and Processors (ASAP), 2012, pp.8-15. pdf
  • Jing Xie, Yu Wang, Yuan Xie, Yield-aware time-efficient testing and self-fixing design for TSV-based 3D ICs , in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp.738-743. pdf
  • Xiaoming Chen, Yu Wang, Huazhong Yang, An adaptive LU factorization algorithm for parallel circuit simulation , in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp.359-364. pdf slide
  • Zuowei Li, Yuchun Ma, Qiang Zhou, Yici Cai, Yu Wang, Tingting Huang, Yuan Xie, Thermal-aware power network design for ir drop reduction in 3d ics , in Proceedings of the 17th Asia and South Pacific Design Automation Conference (ASP-DAC), 2012, pp.47-52. pdf
  • Ling Ren, Xiaoming Chen, Yu Wang, Chenxi Zhang, Huazhong Yang, Sparse LU factorization for parallel circuit simulation on GPU , in Proceedings of the 49th Annual Design Automation Conference (DAC), 2012, pp.1125-1130. pdf slide
  • Wujie Wen, Yaojun Zhang, Yiran Chen, Yu Wang, Yuan Xie, PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method , in Proceedings of the 49th Annual Design Automation Conference (DAC), 2012, pp.1191-1196. pdf
  • Zhaoran Wang, Yu Zhang, Xiaotao Chang, Xiang Mi, Yu Wang, Kun Wang, Huazhong Yang, Pub/Sub on stream: a multi-core based message broker with QoS support , in Proceedings of the 6th ACM International Conference on Distributed Event-Based Systems (DEBS), 2012, pp.127-138.
  • Brahim Betkaoui, Yu Wang, David B Thomas, Wayne Luk, Parallel FPGA-based all pairs shortest paths for sparse networks: A human brain connectome case study , in Proceedings of 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012, pp.99-104. pdf
  • Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang, FPGA based memory efficient high resolution stereo vision system for video tolling , in Proceedings of the International Conference on the Field-Programmable Technology (FPT), 2012, pp.29-32. pdf
  • Mo Xu, Xiaorui Zhang, Yu Wang, Ling Ren, Ziyu Wen, Yi Xu, Gaolang Gong, Ningyi Xu, Huazhong Yang, Probabilistic brain fiber tractography on gpus , in Proceedings of the IEEE 26th International Parallel and Distributed Processing Symposium Workshops PhD Forum (IPDPSW), 2012, pp.742-751. pdf
  • Xiaoming Chen, Yu Wang, Huazhong Yang, Parallel Circuit Simulation on Multi/Many-core Systems , in Proceedings of the IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2012, pp.2530-2533. pdf
  • Guangyu Sun, Yaojun Zhang, Yu Wang, Yiran Chen, Improving energy efficiency of write-asymmetric memories by log style write , in Proceedings of the ACM/IEEE international symposium on Low power electronics and design (ISLPED), 2012, pp.173-178.
  • Hong Luo, Yu Wang, Yu Cao, Yuan Xie, Yuchun Ma, Huazhong Yang, Temporal performance degradation under RTN: Evaluation and mitigation for nanoscale circuits , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2012, pp.183-188. pdf
  • Wei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang, FPGA accelerated parallel sparse matrix factorization for circuit simulations , in Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications (ARC), 2011, pp.302-315. pdf
  • Bei Yu, Sheqin Dong, Yuchun Ma, Tao Lin, Yu Wang, Song Chen, Satoshi Goto, Network flow-based simultaneous retiming and slack budgeting for low power design , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.473-478. pdf
  • Kan Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Jason Cong, Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.261-266. pdf
  • Wulong Liu, Yu Wang, Wei Liu, Yuchun Ma, Yuan Xie, Huazhong Yang, On-chip Hybrid Power Supply System for Wireless Sensor Nodes , in Proceedings of the 16th Asia and South Pacific Design Automation Conference (ASP-DAC), 2011, pp.23:1--23:22. pdf
  • Binjie Song, Shan Zeng, Yuchun Ma, Ning Xu, Yu Wang, Tree-Based Partitioning Approach for Network-on-Chip Synthesis , in Proceedings of the 12th International Conference on Computer-Aided Design and Computer Graphics (CAD/CG) , 2011, pp.465-470.
  • Tianji Wu, Di Wu, Yu Wang, Xiaorui Zhang, Hong Luo, Ningyi Xu, Huazhong Yang, Gemma in April: A matrix-like parallel programming architecture on OpenCL , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2011, pp.1-6. pdf
  • Yu Wang, Mo Xu, Ling Ren, Xiaorui Zhang, Di Wu, Yong He, Ningyi Xu, Huazhong Yang, A heterogeneous accelerator platform for multi-subject voxel-based brain network analysis , in Proceedings of the International Conference on Computer-Aided Design (ICCAD), 2011, pp.339-344. pdf
  • Shouchun Tao, Jia Liu, Yuchun Ma, Zhigang He, Ning Xu, Yu Wang, Xianlong Hong, An ILP algorithm for voltage-island generation considering temperature in 3D-Ics , in Proceddings of the International Conference on Electric Information and Control Engineering (ICEICE), 2011, pp.3950-3953. pdf
  • Hong Luo, Xiaoming Chen, Jyothi Velamala, Yu Wang, Yu Cao, Ch, Vikas ra, Yuchun Ma, Huazhong Yang, Circuit-level delay modeling considering both TDDB and NBTI , in Proceedings of the 12th International Symposium on Quality Electronic Design (ISQED), 2011, pp.1-8. pdf
  • Weichen Liu, Jiang Xu, Xuan Wang, Yu Wang, Wei Zhang, Yaoyao Ye, Xiaowen Wu, Mahdi Nikdast, Zhehui Wang, A hardware-software collaborated method for soft-error tolerant mpsoc , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2011, pp.260-265. pdf
  • Hong Luo, Yu Wang, J Velamala, Yu Cao, Yuan Xie, Huazhong Yang, The impact of correlation between NBTI and TDDB on the performance of digital circuits , in Proceedings of the IEEE 54th International Midwest Symposium on Circuits and Systems (MWSCAS), 2011, pp.1-4. pdf
  • Paul Falkenstern, Yuan Xie, Yao-Wen Chang, Yu Wang, Three-dimensional integrated circuits (3D IC) floorplan and power/ground network co-synthesis , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.169-174. pdf
  • Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, PS-FPG: pattern selection based co-design of floorplan and power/ground network with wiring resource optimization , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.769-774.
  • Shenghua Liu, Yuchun Ma, Xianlong Hong, Yu Wang, Simultaneous slack budgeting and retiming for synchronous circuits optimization , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.49-54.
  • Yibo Chen, Yuan Xie, Yu Wang, Andres Takach, Parametric yield driven resource binding in behavioral synthesis with multi-V th/V dd library , in Proceedings of the 15th Asia and South Pacific Design Automation Conference (ASP-DAC), 2010, pp.781-786. pdf
  • Yu Wang, Yong He, Yi Shan, Tianji Wu, Di Wu, Huazhong Yang, Hardware computing for brain network analysis , in Proceedings of the 2nd Asia Symposium on Quality Electronic Design (ASQED), 2010, pp.219-222. pdf
  • Yi Shan, Bo Wang, Jing Yan, Yu Wang, Ningyi Xu, Huazhong Yang, FPMR: MapReduce framework on FPGA , in Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2010, pp.93-102. pdf
  • Jing Yan, Ning-Yi Xu, Xiong-Fei Cai, Rui Gao, Yu Wang, Rong Luo, Feng-Hsiung Hsu, LambdaRank acceleration for relevance ranking in web search engines , in Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2010, pp.285-285.
  • Zhigang He, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, On handling fixed blocks in incremental fixed-outline floorplanning , in International Conference on Communications, Circuits and Systems (ICCCAS), 2010, pp.876-880.
  • Zeng Wang, Yuchun Ma, Sheqin Dong, Yu Wang, Xianlong Hong, Incremental I/O planning with white space redistribution for flip-chip design , in International Conference on Communications, Circuits and Systems (ICCCAS), 2010, pp.866-870.
  • Yao Wang, Yu Wang, Jiang Xu, Huazhong Yang, Proceedings of the International Conference on Green Circuits and Systems (ICGCS) , in Proceedings of the International Conference on Green Circuits and Systems (ICGCS), 2010, pp.323-327. pdf
  • Shuai Tao, Yu Wang, Jiang Xu, Yuchun Ma, Yuan Xie, Huazhong Yang, Simulation and analysis of P/G noise in TSV based 3D MPSoC , in Proceedings of the International Conference on Green Circuits and Systems (ICGCS), 2010, pp.573-577. pdf
  • Yuchun Ma, Kan Wang, Sheqin Dong, Yu Wang, Xianlong Hong, Thermal effects of leakage power in 3D ICs , in Proceedings of the International Conference on Green Circuits and Systems (ICGCS), 2010, pp.578-583. pdf
  • Di Wu, Tianji Wu, Yi Shan, Yu Wang, Yong He, Ningyi Xu, Huazhong Yang, Making human connectome faster: GPU acceleration of brain network analysis , in Proceedings of the IEEE 16th International Conference on Parallel and Distributed Systems (ICPADS), 2010, pp.593-600. pdf
  • Tianji Wu, Bo Wang, Yi Shan, Feng Yan, Yu Wang, Ningyi Xu, Efficient pagerank and spmv computation on amd gpus , in Proceedings of the 39th International Conference on Parallel Processing (ICPP) , 2010, pp.81-89. pdf
  • Yi Shan, Tianji Wu, Yu Wang, Bo Wang, Zilong Wang, Ningyi Xu, Huazhong Yang, FPGA and GPU implementation of large scale SpMV , in Proceedings of the IEEE 8th Symposium on Application Specific Processors (SASP) , 2010, pp.64-70. pdf
  • Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, Floorplan and Power/Ground network co-design using guided incremental floorplanning , in Proceedings of the IEEE 8th International Conference on ASIC (ASICON), 2009, pp.747-750. pdf
  • Fubing Mao, Yuchun Ma, Ning Xu, Shenghua Liu, Yu Wang, Xianlong Hong, Congestion-driven floorplanning based on two-stage optimization , in Proceedings of the IEEE 8th International Conference on ASIC (ASICON), 2009, pp.1298-1301.
  • Michael DeBole, Krishnan Ramakrishnan, Varsha Balakrishnan, Wenping Wang, Hong Luo, Yu Wang, Yuan Xie, Yu Cao, Narayanan Vijaykrishnan, A framework for estimating NBTI degradation of microarchitectural components , in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2009, pp.455-460. pdf
  • Yu Wang, Jiang Xu, Shengxi Huang, Weichen Liu, Huazhong Yang, A case study of on-chip sensor network in multiprocessor system-on-chip , in Proceedings of the international conference on Compilers, architecture, and synthesis for embedded systems, 2009, pp.241-250.
  • Weichen Liu, Zonghua Gu, Jiang Xu, Yu Wang, Mingxuan Yuan, An efficient technique for analysis of minimal buffer requirements of synchronous dataflow graphs with model checking , in Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis, 2009, pp.61-70.
  • Yu Wang, Xiaoming Chen, Wenping Wang, Yu Cao, Yuan Xie, Huazhong Yang, Gate replacement techniques for simultaneous leakage and aging optimization , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2009, pp.328-333. pdf slide
  • Jing Yan, Ning-Yi Xu, Xiong-Fei Cai, Rui Gao, Yu Wang, Rong Luo, Feng-Hsiung Hsu, FPGA-based acceleration of neural network for ranking in web search engine with a streaming architecture , in Proceedings of the International Conference on Field Programmable Logic and Applications (FPL), 2009, pp.662-665. pdf
  • Fubing Mao, Yuchun Ma, Ning Xu, Xianlong Hong, Yu Wang, Multi-objective floorplanning based on fuzzy logic , in Proceedings of the 6th International Conference on Fuzzy Systems and Knowledge Discovery (FSKD), vol.4, 2009, pp.331-335.
  • Bo Wang, Tianji Wu, Feng Yan, Ruirui Li, Ningyi Xu, Yu Wang, RankBoost Acceleration on both NVIDIA CUDA and ATI Stream platforms , in Proceedings of the 15th International Conference on Parallel and Distributed Systems (ICPADS), 2009, pp.284-291. pdf
  • Bo Zhao, Yu Wang, Huazhong Yang, Hui Wang, The NBTI impact on RF front end in wireless sensor networks , in Proceedings of the IEEE Circuits and Systems International Conference on Testing and Diagnosis (ICTD), 2009, pp.1-4. pdf
  • Xiaoming Chen, Yu Wang, Yu Cao, Yuchun Ma, Huazhong Yang, Variation-aware supply voltage assignment for minimizing circuit degradation and leakage , in Proceedings of the 2009 ACM/IEEE international symposium on Low power electronics and design (ISLPED), 2009, pp.39-44. pdf slide
  • Yu Wang, Xiaoming Chen, Wenping Wang, Varsha Balakrishnan, Yu Cao, Yuan Xie, Huazhong Yang, On the efficacy of input Vector Control to mitigate NBTI effects and leakage power , in Proceedings of the Quality of Electronic Design (ISQED), 2009, pp.19-26. pdf
  • Balaji Vaidyanathan, Anthony S Oates, Yuan Xie, Yu Wang, NBTI-aware statistical circuit delay assessment. , in Proceedings of the International Symposium on Quality Electronic Design (ISQED), 2009, pp.13-18. pdf
  • Yan Xu, Weichen Liu, Yu Wang, Jiang Xu, Xiaoming Chen, Huazhong Yang, On-line mpsoc scheduling considering power gating induced power/ground noise , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009, pp.109-114. pdf
  • Li Li, Yuchun Ma, Ning Xu, Yu Wang, Xianlong Hong, Modern floorplanning with boundary clustering constraint , in Proceedings of the IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2009, pp.79-84.
  • Balaji Vaidyanathan, Yu Wang, Yuan Xie, Cost-aware lifetime yield analysis of heterogeneous 3D on-chip cache , in Proceedings of the IEEE International Workshop on Memory Technolog (MTDT), 2009, pp.65-70. pdf
  • Guangming Yu, Yu Wang, Huazhong Yang, Hui Wang, A fast-locking all-digital phase-locked loop with a novel counter-based mode switching controller , in Proceedings of the TENCON IEEE Region 10 Conference (TENCON), 2009, pp.1-5.
  • Yu Wang, Kai Zhou, Zhonghai Lu, Huazhong Yang, Dynamic TDM virtual circuit implementation for NoC , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2008, pp.1533-1536. pdf
  • Saihua Lin, Yu Wang, Rong Luo, Huazhong Yang, A capacitive boosted buffer technique for high-speed process-variation-tolerant interconnect in udvs application , in Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC), 2008, pp.304-309. pdf
  • Qian Ding, Yu Wang, Hui Wang, Rong Luo, Huazhong Yang, Output remapping technique for soft-error rate reduction in critical paths , in Proceedings of the 9th International Symposium on Quality Electronic Design (ISQED), 2008, pp.74-77. pdf
  • Xukai Shen, Yu Wang, Rong Luo, Huazhong Yang, Leakage power reduction through dual V th assignment considering threshold voltage variation , in Proceedings of the 7th International Conference on ASIC (ASICON), 2007, pp.1122-1125. pdf
  • Yu Wang, Hong Luo, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Temperature-aware NBTI modeling and the impact of input vector control on performance degradation , in Proceedings of the Design, Automation & Test in Europe Conference & Exhibition (DATE), 2007, pp.1-6. pdf
  • Ku He, Rong Luo, Yu Wang, A power gating scheme for ground bounce reduction during mode transition , in Proceedings of the 25th International Conference on Computer Design (ICCD), 2007, pp.388-394.
  • Hong Luo, Yu Wang, Ku He, Rong Luo, Huazhong Yang, Yuan Xie, Modeling of PMOS NBTI effect considering temperature variation , in Proceedings of the 8th International Symposium on Quality Electronic Design (ISQED), 2007, pp.139-144. pdf
  • Yongpan Liu, Yu Wang, Feng Zhang, Rong Luo, Hui Wang, A New Thermal-Conscious System-Level Methodology for Energy-Efficient Processor Voltage Selection , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2006, pp.968-971. pdf
  • Yu Wang, Hui Wang, Huazhong Yang, Fine-grain Sleep Transistor Placement Considering Leakage Feedback Gate , in Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) , 2006, pp.964-967. pdf
  • Yu Wang, Hai Lin, Huazhong Yang, Rong Luo, Hui Wang, Simultaneous fine-grain sleep transistor placement and sizing for leakage optimization , in Proceedings of the 7th International Symposium on Quality Electronic Design (ISQED), 2006, pp.723-728. pdf

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