Kaiyuan Guo (郭开元)
Kaiyuan Guo is a PhD candidate in the Department of Electronic Engineering at Tsinghua University. His research interests include hardware acceleration of deep learning and SLAM. Guo received a BS in electronic engineering from Tsinghua University.
Contact
Address: Room 4-101, Rohm Building, E.E. Dept., Tsinghua University, Beijing, China
Email: gky15☺mail·tsinghua·eduNOSPAMMING·cn
Phone: +86-18810680604
Selected Publications
Journal Articles
- Angel-Eye: A Complete Design Flow for Mapping CNN onto Embedded FPGA , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.37, No.1, 2018, pp.35-47. pdf
- Software–Hardware Codesign for Efficient Neural Network Acceleration , in IEEE Micro, vol.37, No.2, 2017, pp.18-25. pdf
Conference Papers
- Real-time object detection towards high power efficiency , in Design, Automation & Test in Europe Conference & Exhibition (DATE), 2018, pp.704-708. pdf
- RRAM Based Buffer Design for Energy Efficient CNN Accelerator , in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2018, pp.435-440. pdf
- Instruction Driven Cross-Layer CNN Accelerator with Winograd Transformation on FPGA , in ICFPT 2017, 2017, pp.227-230. pdf slide
- Going Deeper with Embedded FPGA Platform for Convolutional Neural Network , in ACM International Symposium on FPGA, 2016, pp.26-35. pdf slide
- SRI-SURF: A Better SURF Powered by Scaled-RAM Interpolator on FPGA , in International Conference on Field-Programmable Logic and Applications (FPL), 2016, pp.1-8. pdf slide
- Angel-Eye: A Complete Design Flow for Mapping CNN onto Customized Hardware , in IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016, pp.24-29. pdf
- A Universal FPGA-based Floating-point Matrix Processor for Mobile Systems , in Proceedings of the International Conference on Field-Programmable Technology (FPT), 2014, pp.139 - 146. pdf
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