Zhenhua Zhu (朱振华)
Address: Room 4-205, Rohm Building, Tsinghua University, Beijing, China
- TIME: A Training-in-memory Architecture for RRAM-based Deep Neural Networks , to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019. pdf
- Learning the Sparsity for ReRAM: Mapping and Pruning Sparse Neural Network for ReRAM based Accelerator , to appear in Proceedings of the 24th Asia and South Pacific Design Automation Conference (ASP-DAC), 2019.
- A Configurable Multi-Precision CNN Computing Framework Based on Single Bit RRAM , in Design Automation Conference (DAC), 2019. pdf slide
- A General Logic Synthesis Framework for Memristor-based Logic Design , to appear in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019.
- Training Low Bitwidth Convolutional Neural Networks on RRAM , in Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, pp.117-122. pdf
- Rescuing Memristor-based Computing with Non-linear Resistance Levels , in DATE 2018, 2018, pp.407-412. pdf
- Mixed Size Crossbar based RRAM CNN Accelerator with Overlapped Mapping Method , in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2018. pdf slide
- TIME:A Training-in-memory Architecture for Memristor-based Deep Neural Network , in Design Automation Conference (DAC), 2017, pp.26:1-26:6. pdf slide
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