Yi Shan (单羿)

Yi Shan is now a senior R&D engineer in IDL of Baidu Inc. Before joining Baidu, he received his B.S. degree in Tsinghua University, China in 2008, and then Ph.D. degree in NICS Group, Electronics Engineering Department, Tsinghua University in 2014, supervised by Prof. Xu Chen (Tsinghua University), Prof. Huazhong Yang (Tsinghua University) and Prof. Wayne Luk (Imperial College London). Dr. Shan's work mainly focuses on heterogeneous parallel/distributed computing based on GPU cluster for deep learning applications, and hardware computing on FPGA for other applications, such as stereo vision, search engine, and brain network analysis.


Address: F4-LOFT, Baidu Building, Institute of Deep Learning, Baidu Inc., Beijing, 100085, China
Email: shany04☺gmNOSPAMMINGail·com
Phone: +86 13810986576

Selected Publications

Journal Articles

  • Boxun Li, Peng Gu, Yi Shan, Yu Wang, Yiran Chen, Huazhong Yang, RRAM-based Analog Approximate Computing , in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol.34, No.12, 2015, pp.1905-1917. pdf
  • Yi Shan, Yuchen Hao, Wenqiang Wang, Yu Wang, Xu Chen, Huazhong Yang, Wayne Luk, Hardware Acceleration for an Accurate Stereo Vision System Using Mini-Census Adaptive Support Region , in ACM Transactions on Embedded Computing Systems (TECS), vol.13, No.4s, 2014, pp.132:1-132:24. pdf

Conference Papers

  • Fei Chen, Yi Shan, Yu Zhang, Yu Wang, Hubertus Franke, Xiaotao Chang, Kun Wang, Enabling FPGAs in the Cloud , in Proceedings of the 11th ACM Conference on Computing Frontiers, 2014, pp.3:1-3:10. pdf
  • Guohao Dai, Yi Shan, Fei Chen, Yu Zhang, Yu Wang, Kun Wang and Huazhong Yang, Online Scheduling for FPGA Computation in the Cloud , in International Conference on Field-Programmable Technology (FPT), 2014, pp.330-333. pdf
  • Boxun Li, Yi Shan, Miao Hu, Yu Wang, Yiran Chen, Huazhong Yang, Memristor-based approximated computation , in Proceedings of the International Symposium on Low Power Electronics and Design (ISLPED), 2013, pp.242-247. pdf
  • Yi Shan, Zilong Wang, Wenqiang Wang, Yuchen Hao, Yu Wang, Kuen Hung Tsoi, Wayne Luk, Huazhong Yang, FPGA based memory efficient high resolution stereo vision system for video tolling , in Proceedings of the International Conference on the Field-Programmable Technology (FPT), 2012, pp.29-32. pdf
  • Wei Wu, Yi Shan, Xiaoming Chen, Yu Wang, Huazhong Yang, FPGA accelerated parallel sparse matrix factorization for circuit simulations , in Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications (ARC), 2011, pp.302-315. pdf
  • Yu Wang, Yong He, Yi Shan, Tianji Wu, Di Wu, Huazhong Yang, Hardware computing for brain network analysis , in Proceedings of the 2nd Asia Symposium on Quality Electronic Design (ASQED), 2010, pp.219-222. pdf
  • Yi Shan, Bo Wang, Jing Yan, Yu Wang, Ningyi Xu, Huazhong Yang, FPMR: MapReduce framework on FPGA , in Proceedings of the 18th Annual ACM/SIGDA International Symposium on Field Programmable Gate Arrays (FPGA), 2010, pp.93-102. pdf
  • Di Wu, Tianji Wu, Yi Shan, Yu Wang, Yong He, Ningyi Xu, Huazhong Yang, Making human connectome faster: GPU acceleration of brain network analysis , in Proceedings of the IEEE 16th International Conference on Parallel and Distributed Systems (ICPADS), 2010, pp.593-600. pdf
  • Tianji Wu, Bo Wang, Yi Shan, Feng Yan, Yu Wang, Ningyi Xu, Efficient pagerank and spmv computation on amd gpus , in Proceedings of the 39th International Conference on Parallel Processing (ICPP) , 2010, pp.81-89. pdf
  • Yi Shan, Tianji Wu, Yu Wang, Bo Wang, Zilong Wang, Ningyi Xu, Huazhong Yang, FPGA and GPU implementation of large scale SpMV , in Proceedings of the IEEE 8th Symposium on Application Specific Processors (SASP) , 2010, pp.64-70. pdf

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