Yi Cai (蔡熠)
Address: 4-205, Rohm Building, Tsinghua University, Beijing, China
- TIME: A Training-in-memory Architecture for RRAM-based Deep Neural Networks , to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2019. pdf
- Low Bit-width Convolutional Neural Network on RRAM , to appear in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.
- Enabling Secure in-Memory Neural Network Computing by Sparse Fast Gradient Encryption , to appear in IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2019.
- Training Low Bitwidth Convolutional Neural Networks on RRAM , in Proceedings of the 23rd Asia and South Pacific Design Automation Conference (ASP-DAC), 2018, pp.117-122. pdf
- Long Live TIME: Improving Lifetime for Training-In-Memory Engines by Structured Gradient Sparsification , in Design Automation Conference (DAC), 2018. pdf
- Rescuing Memristor-based Computing with Non-linear Resistance Levels , in DATE 2018, 2018, pp.407-412. pdf
- TIME:A Training-in-memory Architecture for Memristor-based Deep Neural Network , in Design Automation Conference (DAC), 2017, pp.26:1-26:6. pdf slide
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